Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Cosimo Aprile; Thomas Morf; Marcel Kossel; Alessandro Cevrero; Ilter Ozkaya; Thomas Toifl; Yusuf Leblebici

doi:10.1109/ISCAS.2018.8350924

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel Kossel, Alessandro Cevrero, Ilter Ozkaya, Thomas Toifl, Yusuf Leblebici

Department of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analog-to-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538648810
DOIs	https://doi.org/10.1109/ISCAS.2018.8350924
State	Published - 26 Apr 2018
Event	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy Duration: 27 May 2018 → 30 May 2018

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2018-May
ISSN (Print)	0271-4310

Conference

Conference	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Country/Territory	Italy
City	Florence
Period	27/05/18 → 30/05/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

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10.1109/ISCAS.2018.8350924

Cite this

Kim, G., Kull, L., Luu, D., Braendli, M., Menolfi, C., Francese, P. A., Aprile, C., Morf, T., Kossel, M., Cevrero, A., Ozkaya, I., Toifl, T., & Leblebici, Y. (2018). Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings Article 8350924 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8350924

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title = "Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver",

abstract = "This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analog-to-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.",

author = "Gain Kim and Lukas Kull and Danny Luu and Matthias Braendli and Christian Menolfi and Francese, \{Pier Andrea\} and Cosimo Aprile and Thomas Morf and Marcel Kossel and Alessandro Cevrero and Ilter Ozkaya and Thomas Toifl and Yusuf Leblebici",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

year = "2018",

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day = "26",

doi = "10.1109/ISCAS.2018.8350924",

language = "English",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Kim, G, Kull, L, Luu, D, Braendli, M, Menolfi, C, Francese, PA, Aprile, C, Morf, T, Kossel, M, Cevrero, A, Ozkaya, I, Toifl, T & Leblebici, Y 2018, Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8350924, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2018-May, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8350924

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. / Kim, Gain; Kull, Lukas; Luu, Danny et al.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8350924 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Kim, Gain

AU - Kull, Lukas

AU - Luu, Danny

AU - Braendli, Matthias

AU - Menolfi, Christian

AU - Francese, Pier Andrea

AU - Aprile, Cosimo

AU - Morf, Thomas

AU - Kossel, Marcel

AU - Cevrero, Alessandro

AU - Ozkaya, Ilter

AU - Toifl, Thomas

AU - Leblebici, Yusuf

PY - 2018/4/26

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N2 - This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analog-to-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.

AB - This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analog-to-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.

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BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018

Y2 - 27 May 2018 through 30 May 2018

ER -

Kim G, Kull L, Luu D, Braendli M, Menolfi C, Francese PA et al. Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. 8350924. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2018.8350924

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

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