TY - GEN
T1 - Limiting worst-case end-to-end latency when traffic increases in a switched avionics network
AU - Nam, Min Young
AU - Seo, Eunsoo
AU - Sha, Lui
AU - Park, Kyung Joon
AU - Kang, Kyungtae
PY - 2011
Y1 - 2011
N2 - New features are often added incrementally to avionics systems. This avoids redesign and recertification but still requires verifying the timing constraints of both new and existing applications. We introduce a new switch that facilitates this verification by bounding the latency of end-to-end communication across a network. Our clock-driven real-time switching algorithm is throughput-optimal with a bounded worst-case delay for all feasible traffic. Associated heuristics can verify whether the timing constraints of an avionics network are met, after new features have caused traffic to increase, and then search for alternative network configurations if necessary. We show how these heuristics cope with changes to an example environmental monitoring architecture within an avionics system that incorporates our switch. Our approach to analysis can be used to determine, quickly but rigorously, which system architecture meet timing constraints; and it allows the system architect to manage the cascading effects of component changes in a comprehensive manner.
AB - New features are often added incrementally to avionics systems. This avoids redesign and recertification but still requires verifying the timing constraints of both new and existing applications. We introduce a new switch that facilitates this verification by bounding the latency of end-to-end communication across a network. Our clock-driven real-time switching algorithm is throughput-optimal with a bounded worst-case delay for all feasible traffic. Associated heuristics can verify whether the timing constraints of an avionics network are met, after new features have caused traffic to increase, and then search for alternative network configurations if necessary. We show how these heuristics cope with changes to an example environmental monitoring architecture within an avionics system that incorporates our switch. Our approach to analysis can be used to determine, quickly but rigorously, which system architecture meet timing constraints; and it allows the system architect to manage the cascading effects of component changes in a comprehensive manner.
UR - http://www.scopus.com/inward/record.url?scp=84855565535&partnerID=8YFLogxK
U2 - 10.1109/RTCSA.2011.9
DO - 10.1109/RTCSA.2011.9
M3 - Conference contribution
AN - SCOPUS:84855565535
SN - 9780769545028
T3 - Proceedings - 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
SP - 285
EP - 294
BT - Proceedings - 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
T2 - 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
Y2 - 28 August 2011 through 31 August 2011
ER -