TY - JOUR
T1 - Image Recognition Accelerator Design Using In-Memory Processing
AU - Kim, Yeseong
AU - Imani, Mohsen
AU - Rosing, Tajana Simunic
N1 - Publisher Copyright:
© 1981-2012 IEEE.
PY - 2019/1/1
Y1 - 2019/1/1
N2 - This paper proposes a hardware accelerator design, called object recognition and classification hardware accelerator on resistive devices, which processes object recognition tasks inside emerging nonvolatile memory. The in-memory processing dramatically lowers the overhead of data movement, improving overall system efficiency. The proposed design accelerates key subtasks of image recognition, including text, face, pedestrian, and vehicle recognition. The evaluation shows significant improvements on performance and energy efficiency as compared to state-of-the-art processors and accelerators.
AB - This paper proposes a hardware accelerator design, called object recognition and classification hardware accelerator on resistive devices, which processes object recognition tasks inside emerging nonvolatile memory. The in-memory processing dramatically lowers the overhead of data movement, improving overall system efficiency. The proposed design accelerates key subtasks of image recognition, including text, face, pedestrian, and vehicle recognition. The evaluation shows significant improvements on performance and energy efficiency as compared to state-of-the-art processors and accelerators.
UR - http://www.scopus.com/inward/record.url?scp=85058999661&partnerID=8YFLogxK
U2 - 10.1109/MM.2018.2889402
DO - 10.1109/MM.2018.2889402
M3 - Article
AN - SCOPUS:85058999661
SN - 0272-1732
VL - 39
SP - 17
EP - 23
JO - IEEE Micro
JF - IEEE Micro
IS - 1
M1 - 8587206
ER -
