Hardware architecture design and implementation for FMCW radar signal processing algorithm

Hyun Eugin; Jonghun Lee

doi:10.1109/DASIP.2014.7115643

Hardware architecture design and implementation for FMCW radar signal processing algorithm

Division of Automotive Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target; even more computational complexity is required. In this paper, we report on how a newly developed signal processing module is implemented in the FPGA, and on its performance measured under test conditions. Moreover, we have presented results from analysis of the use of hardware resources and processing times.

Original language	English
Title of host publication	DASIP 2014 - Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing
Editors	Ana Pinzari, Adam Morawiec
Publisher	IEEE Computer Society
ISBN (Electronic)	9791092279054
DOIs	https://doi.org/10.1109/DASIP.2014.7115643
State	Published - 29 May 2015
Event	2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014 - Madrid, Spain Duration: 8 Oct 2014 → 10 Oct 2014

Publication series

Name	Conference on Design and Architectures for Signal and Image Processing, DASIP
Volume	2015-May
ISSN (Print)	2164-9766

Conference

Conference	2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014
Country/Territory	Spain
City	Madrid
Period	8/10/14 → 10/10/14

Bibliographical note

Publisher Copyright:
© 2014 European Electronic Chips & Systems design Initiative - ECSI.

Keywords

FMCW radar
chirp sequence
detection algorithm

Access to Document

10.1109/DASIP.2014.7115643

Cite this

Eugin, H., & Lee, J. (2015). Hardware architecture design and implementation for FMCW radar signal processing algorithm. In A. Pinzari, & A. Morawiec (Eds.), DASIP 2014 - Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing Article 7115643 (Conference on Design and Architectures for Signal and Image Processing, DASIP; Vol. 2015-May). IEEE Computer Society. https://doi.org/10.1109/DASIP.2014.7115643

Eugin, Hyun ; Lee, Jonghun. / Hardware architecture design and implementation for FMCW radar signal processing algorithm. DASIP 2014 - Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing. editor / Ana Pinzari ; Adam Morawiec. IEEE Computer Society, 2015. (Conference on Design and Architectures for Signal and Image Processing, DASIP).

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title = "Hardware architecture design and implementation for FMCW radar signal processing algorithm",

abstract = "Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target; even more computational complexity is required. In this paper, we report on how a newly developed signal processing module is implemented in the FPGA, and on its performance measured under test conditions. Moreover, we have presented results from analysis of the use of hardware resources and processing times.",

keywords = "FMCW radar, chirp sequence, detection algorithm",

author = "Hyun Eugin and Jonghun Lee",

note = "Publisher Copyright: {\textcopyright} 2014 European Electronic Chips \& Systems design Initiative - ECSI.; 2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014 ; Conference date: 08-10-2014 Through 10-10-2014",

year = "2015",

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language = "English",

series = "Conference on Design and Architectures for Signal and Image Processing, DASIP",

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Eugin, H & Lee, J 2015, Hardware architecture design and implementation for FMCW radar signal processing algorithm. in A Pinzari & A Morawiec (eds), DASIP 2014 - Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing., 7115643, Conference on Design and Architectures for Signal and Image Processing, DASIP, vol. 2015-May, IEEE Computer Society, 2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014, Madrid, Spain, 8/10/14. https://doi.org/10.1109/DASIP.2014.7115643

Hardware architecture design and implementation for FMCW radar signal processing algorithm. / Eugin, Hyun ; Lee, Jonghun.
DASIP 2014 - Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing. ed. / Ana Pinzari; Adam Morawiec. IEEE Computer Society, 2015. 7115643 (Conference on Design and Architectures for Signal and Image Processing, DASIP; Vol. 2015-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Lee, Jonghun

PY - 2015/5/29

Y1 - 2015/5/29

N2 - Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target; even more computational complexity is required. In this paper, we report on how a newly developed signal processing module is implemented in the FPGA, and on its performance measured under test conditions. Moreover, we have presented results from analysis of the use of hardware resources and processing times.

AB - Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target; even more computational complexity is required. In this paper, we report on how a newly developed signal processing module is implemented in the FPGA, and on its performance measured under test conditions. Moreover, we have presented results from analysis of the use of hardware resources and processing times.

KW - FMCW radar

KW - chirp sequence

KW - detection algorithm

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U2 - 10.1109/DASIP.2014.7115643

DO - 10.1109/DASIP.2014.7115643

M3 - Conference contribution

AN - SCOPUS:84942279113

T3 - Conference on Design and Architectures for Signal and Image Processing, DASIP

BT - DASIP 2014 - Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

A2 - Pinzari, Ana

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PB - IEEE Computer Society

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Eugin H , Lee J. Hardware architecture design and implementation for FMCW radar signal processing algorithm. In Pinzari A, Morawiec A, editors, DASIP 2014 - Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing. IEEE Computer Society. 2015. 7115643. (Conference on Design and Architectures for Signal and Image Processing, DASIP). doi: 10.1109/DASIP.2014.7115643

Hardware architecture design and implementation for FMCW radar signal processing algorithm

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Keywords

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