Design optimization of polyphase digital down converters for extremely high frequency wireless communications

Gain Kim; Raffaele Capoccia; Yusuf Leblebici

doi:10.1109/VLSI-SoC.2015.7314417

Design optimization of polyphase digital down converters for extremely high frequency wireless communications

Gain Kim, Raffaele Capoccia, Yusuf Leblebici

Department of Electrical Engineering and Computer Science

Swiss Federal Institute of Technology Lausanne

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

In this paper, an area-optimized polyphase digital down converter (DDC) architecture is introduced, where the mixers can be completely merged into the polyphase decimation filter under certain conditions. We also introduce an interface architecture, called synchronizer, between the back-end of an extremely high-speed time interleaved ADC (TI-ADC) and the front-end of a polyphase DDC. The synchronizer enables safe downsampling for a polyphase DDC, when the TI-ADC's sampling rate is above tens of GS/s. We show that the proposed interface architecture prevents any potential timing constraint violations that might occur in the interface between a TI-ADC and a polyphase DDC for extremely high frequency (EHF) wireless communication applications.

Original language	English
Title of host publication	2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
Publisher	IEEE Computer Society
Pages	207-212
Number of pages	6
ISBN (Electronic)	9781467391405
DOIs	https://doi.org/10.1109/VLSI-SoC.2015.7314417
State	Published - 30 Oct 2015
Event	23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 - Daejeon, Korea, Republic of Duration: 5 Oct 2015 → 7 Oct 2015

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Volume	2015-October
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
Country/Territory	Korea, Republic of
City	Daejeon
Period	5/10/15 → 7/10/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Access to Document

10.1109/VLSI-SoC.2015.7314417

Cite this

Kim, G., Capoccia, R., & Leblebici, Y. (2015). Design optimization of polyphase digital down converters for extremely high frequency wireless communications. In 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 (pp. 207-212). Article 7314417 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2015-October). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2015.7314417

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Kim, G, Capoccia, R & Leblebici, Y 2015, Design optimization of polyphase digital down converters for extremely high frequency wireless communications. in 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015., 7314417, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, vol. 2015-October, IEEE Computer Society, pp. 207-212, 23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, Republic of, 5/10/15. https://doi.org/10.1109/VLSI-SoC.2015.7314417

Design optimization of polyphase digital down converters for extremely high frequency wireless communications. / Kim, Gain; Capoccia, Raffaele; Leblebici, Yusuf.
2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015. IEEE Computer Society, 2015. p. 207-212 7314417 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2015-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Kim G, Capoccia R, Leblebici Y. Design optimization of polyphase digital down converters for extremely high frequency wireless communications. In 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015. IEEE Computer Society. 2015. p. 207-212. 7314417. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC.2015.7314417

Design optimization of polyphase digital down converters for extremely high frequency wireless communications

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