Abstract
This paper presents the design and analysis of a serial link transceiver (TRX) architecture employing analog multi-tone signaling for chip-to-chip communication. Multi-tone single-sideband signaling scheme is proposed in TRX architecture in order to optimize bandwidth requirements for each sub-channel and to improve signal-to-noise ratio by reducing inter-channel interferences (ICI) between neighboring sub-channels. System-level modeling results show that the proposed TRX architecture enables equalizer-free communication at 16 Gb/s over a lossy backplane channel that exhibits 22-dB attenuation at 8 GHz, while conventional non-return-to-zero signaling TRX necessitates a two-stage continuous-time linear equalizer. A channel frequency-response inversion scheme, the up/down-conversion mechanism of the TX/RX data stream and the RX design considerations have been analyzed and investigated by architectural modeling.
| Original language | English |
|---|---|
| Article number | 8012494 |
| Pages (from-to) | 3192-3201 |
| Number of pages | 10 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Volume | 64 |
| Issue number | 12 |
| DOIs | |
| State | Published - Dec 2017 |
Bibliographical note
Publisher Copyright:© 2017 IEEE.
Keywords
- Analog multi-tone (AMT)
- Inter-channel interference (ICI)
- Inter-symbol interference (ISI)
- Non-return-to-zero (NRZ) signaling
- Serial-data transceiver (TRX)
- Single-sideband (SSB)