Area Optimization of the Feed-Forward Equalizer for ADC-Based High-Speed Wireline Receiver Using Channel Characteristics

In high-speed serial link, the analog-digital converter (ADC)-based receiver (RX) architecture has been widely applied with 4-level pulse amplitude modulation (PAM-4) for> 56 Gb/s/lane. While ADC-based RXs exhibit strong equalization capability, the feed-forward equalizer (FFE) in its digital signal processor (DSP) occupies a large area due to the large number of multipliers required to implement the parallel finite impulse response (FIR) filter. In this work, we explore the required number of bits for the FFE coefficients depending on the tap position given a chip-to-chip channel profile. By proper bit-level optimization of the FFE multipliers, 42 % of the FFE area could be saved for the twelve largest FFE tap values as compared to the case where the same-sized FFE multipliers are considered for a channel exhibiting 28 dB of loss at 28 GHz.