Abstract
This paper presents a versatile and fast time-domain architectural modeling framework for high-speed serial data transceivers (TRX) that can employ various analog modulation schemes. We highlight a modeling of TRXs employing an analog multi-tone signaling, which is not straightforward to model and hard to optimize with conventional serial link modeling tools. A method to limit the computing system's memory usage when simulating a data transmission of a long bit-stream, e.g., greater than 10 Mbits, is also described. The reliability of the modeling framework is proven by some comparisons with a highly-trusted commercial tool for a conventional TRX architecture.
Original language | English |
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Title of host publication | PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 301-304 |
Number of pages | 4 |
ISBN (Electronic) | 9781509065073 |
DOIs | |
State | Published - 10 Jul 2017 |
Event | 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017 - Giardini Naxos - Taormina, Italy Duration: 12 Jun 2017 → 15 Jun 2017 |
Publication series
Name | PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings |
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Conference
Conference | 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017 |
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Country/Territory | Italy |
City | Giardini Naxos - Taormina |
Period | 12/06/17 → 15/06/17 |
Bibliographical note
Publisher Copyright:© 2017 IEEE.