An efficient H/W architecture for a UWB pulse Doppler radar system

In this paper, we suggest efficient structures of radar in order to reduce the hardware complexity associated with UWB radar. The conventional type of pulse Doppler radar should be computing by the fast Fourier transform (FFT) of all range gates independently in order to analyze the characteristics of the Doppler signals. We observe that this method requires a huge block to perform FFT of all of the range gates. Therefore, instead of analyzing the Doppler characteristics of all of the range gates, the proposed architecture classifies the tasks into targets and noise among all range gates in advance and then extracts the Doppler of the targets. The key ideas in this paper focus on reducing the number of FFT instances to process the targets in the received signal. According to the results of simulations conducted to verify the proposed method, although the detection performance of the proposed architecture is identical to that of the conventional architecture, the proposed structures can reduce the hardware complexity by at least 76.4 percent compared to the conventional method.