An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm

Hanho Choi; Ha Il Song; Hyosup Won; Junyoung Yoo; Woohyun Kwon; Huxian Jin; Konan Kwon; Cheongmin Lee; Gain Kim; Jake Eu; Sean Park; Hyeon Min Bae

doi:10.1109/ESSCIRC59616.2023.10268802

An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm

Hanho Choi
, Ha Il Song
, Hyosup Won
, Junyoung Yoo
, Woohyun Kwon
, Huxian Jin
, Konan Kwon
, Cheongmin Lee
, Gain Kim
, Jake Eu
, Sean Park
, Hyeon Min Bae

Department of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents an 86. 71875GHz R transceiver IC featuring a fully integrated clock and data recovery (CDR)-assisted carrier synchronization loop for waveguide links. The IC fabricated in 28nm CMOS demonstrates 57. 8125Gb/s PAM-4 data transmission over a 1. 5m waveguide channel. The proposed carrier synchronization can be achieved only by using a base-band CDR without using power-and-area-hungry RF circuits. The test chip achieves the best figure of merit (FoM) of 3. 5pJ/b/m in terms of throughput-distance, and energy efficiency compared to the prior art.

Original language	English
Title of host publication	ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference
Publisher	IEEE Computer Society
Pages	181-184
Number of pages	4
ISBN (Electronic)	9798350304206
DOIs	https://doi.org/10.1109/ESSCIRC59616.2023.10268802
State	Published - 2023
Event	49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 - Lisbon, Portugal Duration: 11 Sep 2023 → 14 Sep 2023

Publication series

Name	European Solid-State Circuits Conference
Volume	2023-September
ISSN (Print)	1930-8833

Conference

Conference	49th IEEE European Solid State Circuits Conference, ESSCIRC 2023
Country/Territory	Portugal
City	Lisbon
Period	11/09/23 → 14/09/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

CDR
Phase-locked loop (PLL)
RF transceiver
Waveguide link
carrier synchronization

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ESSCIRC59616.2023.10268802

Cite this

Choi, H., Song, H. I., Won, H., Yoo, J., Kwon, W., Jin, H., Kwon, K., Lee, C., Kim, G., Eu, J., Park, S., & Bae, H. M. (2023). An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm. In ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference (pp. 181-184). (European Solid-State Circuits Conference; Vol. 2023-September). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC59616.2023.10268802

@inproceedings{abf2d5d449584330ac85fa1168b1947f,

title = "An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm",

abstract = "This paper presents an 86. 71875GHz R transceiver IC featuring a fully integrated clock and data recovery (CDR)-assisted carrier synchronization loop for waveguide links. The IC fabricated in 28nm CMOS demonstrates 57. 8125Gb/s PAM-4 data transmission over a 1. 5m waveguide channel. The proposed carrier synchronization can be achieved only by using a base-band CDR without using power-and-area-hungry RF circuits. The test chip achieves the best figure of merit (FoM) of 3. 5pJ/b/m in terms of throughput-distance, and energy efficiency compared to the prior art.",

keywords = "CDR, Phase-locked loop (PLL), RF transceiver, Waveguide link, carrier synchronization",

author = "Hanho Choi and Song, \{Ha Il\} and Hyosup Won and Junyoung Yoo and Woohyun Kwon and Huxian Jin and Konan Kwon and Cheongmin Lee and Gain Kim and Jake Eu and Sean Park and Bae, \{Hyeon Min\}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 ; Conference date: 11-09-2023 Through 14-09-2023",

year = "2023",

doi = "10.1109/ESSCIRC59616.2023.10268802",

language = "English",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "181--184",

booktitle = "ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference",

}

Choi, H, Song, HI, Won, H, Yoo, J, Kwon, W, Jin, H, Kwon, K, Lee, C, Kim, G, Eu, J, Park, S & Bae, HM 2023, An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm. in ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference. European Solid-State Circuits Conference, vol. 2023-September, IEEE Computer Society, pp. 181-184, 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, 11/09/23. https://doi.org/10.1109/ESSCIRC59616.2023.10268802

An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm. / Choi, Hanho; Song, Ha Il; Won, Hyosup et al.
ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference. IEEE Computer Society, 2023. p. 181-184 (European Solid-State Circuits Conference; Vol. 2023-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm

AU - Choi, Hanho

AU - Song, Ha Il

AU - Won, Hyosup

AU - Yoo, Junyoung

AU - Kwon, Woohyun

AU - Jin, Huxian

AU - Kwon, Konan

AU - Lee, Cheongmin

AU - Kim, Gain

AU - Eu, Jake

AU - Park, Sean

AU - Bae, Hyeon Min

PY - 2023

Y1 - 2023

N2 - This paper presents an 86. 71875GHz R transceiver IC featuring a fully integrated clock and data recovery (CDR)-assisted carrier synchronization loop for waveguide links. The IC fabricated in 28nm CMOS demonstrates 57. 8125Gb/s PAM-4 data transmission over a 1. 5m waveguide channel. The proposed carrier synchronization can be achieved only by using a base-band CDR without using power-and-area-hungry RF circuits. The test chip achieves the best figure of merit (FoM) of 3. 5pJ/b/m in terms of throughput-distance, and energy efficiency compared to the prior art.

AB - This paper presents an 86. 71875GHz R transceiver IC featuring a fully integrated clock and data recovery (CDR)-assisted carrier synchronization loop for waveguide links. The IC fabricated in 28nm CMOS demonstrates 57. 8125Gb/s PAM-4 data transmission over a 1. 5m waveguide channel. The proposed carrier synchronization can be achieved only by using a base-band CDR without using power-and-area-hungry RF circuits. The test chip achieves the best figure of merit (FoM) of 3. 5pJ/b/m in terms of throughput-distance, and energy efficiency compared to the prior art.

KW - CDR

KW - Phase-locked loop (PLL)

KW - RF transceiver

KW - Waveguide link

KW - carrier synchronization

UR - https://www.scopus.com/pages/publications/85175240342

U2 - 10.1109/ESSCIRC59616.2023.10268802

DO - 10.1109/ESSCIRC59616.2023.10268802

M3 - Conference contribution

AN - SCOPUS:85175240342

T3 - European Solid-State Circuits Conference

SP - 181

EP - 184

BT - ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference

PB - IEEE Computer Society

T2 - 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023

Y2 - 11 September 2023 through 14 September 2023

ER -

An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm

Abstract

Publication series

Conference

Bibliographical note

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this