Abstract
This paper presents a versatile and fast time-domain architectural modeling framework for high-speed serial data transceivers (TRX) that can employ various analog modulation schemes. We highlight a modeling of TRXs employing an analog multi-tone signaling, which is not straightforward to model and hard to optimize with conventional serial link modeling tools. A method to limit the computing system's memory usage when simulating a data transmission of a long bit-stream, e.g., > 10 Mbits, is also described. The reliability of the modeling framework is proven by some comparisons with a highly-trusted commercial tool for a conventional TRX architecture.
| Original language | English |
|---|---|
| Title of host publication | 2025 International Conference on Electronics, Information, and Communication, ICEIC 2025 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798331510756 |
| DOIs | |
| State | Published - 2025 |
| Event | 2025 International Conference on Electronics, Information, and Communication, ICEIC 2025 - Osaka, Japan Duration: 19 Jan 2025 → 22 Jan 2025 |
Publication series
| Name | 2025 International Conference on Electronics, Information, and Communication, ICEIC 2025 |
|---|
Conference
| Conference | 2025 International Conference on Electronics, Information, and Communication, ICEIC 2025 |
|---|---|
| Country/Territory | Japan |
| City | Osaka |
| Period | 19/01/25 → 22/01/25 |
Bibliographical note
Publisher Copyright:© 2025 IEEE.
Keywords
- analog multitone
- non-return to zero
- PAM-4
- serial link
- Serial link modeling
- statistical modeling
- wireline transceiver
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