A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption

Seok Jae Lee; Ji Woong Choi; Seon Wook Kim; Jongsun Park

doi:10.1109/TVLSI.2010.2088142

A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption

Seok Jae Lee, Ji Woong Choi, Seon Wook Kim, Jongsun Park

Department of Electrical Engineering and Computer Science

Korea University

Research output: Contribution to journal › Article › peer-review

43 Scopus citations

Abstract

This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the filter coefficients and inputs, the proposed FIR filter dynamically changes the filter order. Mathematical analysis on power savings and filter performance degradation and its experimental results show that the proposed approach achieves significant power savings without seriously compromising the filter performance. The power savings is up to 41.9% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3% compared to the conventional approach.

Original language	English
Article number	5640702
Pages (from-to)	2221-2228
Number of pages	8
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	19
Issue number	12
DOIs	https://doi.org/10.1109/TVLSI.2010.2088142
State	Published - Dec 2011

Bibliographical note

Funding Information:
Manuscript received January 28, 2010; revised June 19, 2010 and August 20, 2010; accepted September 19, 2010. Date of publication November 18, 2010; date of current version October 28, 2011. This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0004484) and in part by a Korea University Grant.

Keywords

Approximate filtering
low power filter
reconfigurable design

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10.1109/TVLSI.2010.2088142

Cite this

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title = "A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption",

abstract = "This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the filter coefficients and inputs, the proposed FIR filter dynamically changes the filter order. Mathematical analysis on power savings and filter performance degradation and its experimental results show that the proposed approach achieves significant power savings without seriously compromising the filter performance. The power savings is up to 41.9\% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3\% compared to the conventional approach.",

keywords = "Approximate filtering, low power filter, reconfigurable design",

author = "Lee, \{Seok Jae\} and Choi, \{Ji Woong\} and Kim, \{Seon Wook\} and Jongsun Park",

note = "Funding Information: Manuscript received January 28, 2010; revised June 19, 2010 and August 20, 2010; accepted September 19, 2010. Date of publication November 18, 2010; date of current version October 28, 2011. This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0004484) and in part by a Korea University Grant.",

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doi = "10.1109/TVLSI.2010.2088142",

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AU - Kim, Seon Wook

AU - Park, Jongsun

N1 - Funding Information: Manuscript received January 28, 2010; revised June 19, 2010 and August 20, 2010; accepted September 19, 2010. Date of publication November 18, 2010; date of current version October 28, 2011. This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0004484) and in part by a Korea University Grant.

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N2 - This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the filter coefficients and inputs, the proposed FIR filter dynamically changes the filter order. Mathematical analysis on power savings and filter performance degradation and its experimental results show that the proposed approach achieves significant power savings without seriously compromising the filter performance. The power savings is up to 41.9% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3% compared to the conventional approach.

AB - This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the filter coefficients and inputs, the proposed FIR filter dynamically changes the filter order. Mathematical analysis on power savings and filter performance degradation and its experimental results show that the proposed approach achieves significant power savings without seriously compromising the filter performance. The power savings is up to 41.9% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3% compared to the conventional approach.

KW - Approximate filtering

KW - low power filter

KW - reconfigurable design

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JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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M1 - 5640702

ER -

A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption

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Keywords

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