A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC

This paper addresses the challenges of voltage-sensing read operations on a PRAM-based 1S1R crossbar array, which can be used for MAC operations in processing-inmemory architectures. The nonlinearity of the readout voltage due to the parallel resistance of the accessed cells leads to a narrow sensing margin. Moreover, the SAR ADC widely used in the readout circuits for area and power efficiency leads to high latency. To overcome these challenges, we introduce active feedback using a Gilbert multiplier to the bitline (BL) structure to regulate the resistance of the BL transmission gate and an input-aware SAR logic to optimize the conversion time. The proposed macro design in a 65nm process achieves a 3.79x voltage sensing margin with a Gilbert multiplier under a 3x3 kernel convolution operation. Furthermore, a 6-bit input-aware SAR ADC reduces average latency from 6 to 4.4 clock cycles.