A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS

Jong Hyeok Yoon; Soon Won Kwon; Hyeon Min Bae

doi:10.1109/CICC.2015.7338486

A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS

Jong Hyeok Yoon
, Soon Won Kwon
, Hyeon Min Bae

Department of Electrical Engineering and Computer Science

Korea Advanced Institute of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

A DC-to-12.5Gb/s all-rate CDR IC with a single LC VCO is fabricated in 90nm CMOS. Static fractional dividers with an asynchronous phase calibration scheme are employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme which adjusts the bandwidth of a CDR automatically in the background for optimum BER performance by monitoring the phase difference between the incoming data and the recovered clock signal. The proposed CDR supports reference-less all-rate operation and compensates for 20dB of channel loss using a CTLE, a one-tap DFE and a three-tap pre-emphasis filter. The power efficiency of the test chip is 4.88mW/Gb/s.

Original language	English
Title of host publication	2015 IEEE Custom Integrated Circuits Conference, CICC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479986828
DOIs	https://doi.org/10.1109/CICC.2015.7338486
State	Published - 25 Nov 2015
Event	IEEE Custom Integrated Circuits Conference, CICC 2015 - San Jose, United States Duration: 28 Sep 2015 → 30 Sep 2015

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2015-November
ISSN (Print)	0886-5930

Conference

Conference	IEEE Custom Integrated Circuits Conference, CICC 2015
Country/Territory	United States
City	San Jose
Period	28/09/15 → 30/09/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

All-rate CDR
asynchronous calibration loop
automatic loop gain calibration
static fractional divider

Access to Document

10.1109/CICC.2015.7338486

Cite this

Yoon, J. H., Kwon, S. W., & Bae, H. M. (2015). A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS. In 2015 IEEE Custom Integrated Circuits Conference, CICC 2015 Article 7338486 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2015-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2015.7338486

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abstract = "A DC-to-12.5Gb/s all-rate CDR IC with a single LC VCO is fabricated in 90nm CMOS. Static fractional dividers with an asynchronous phase calibration scheme are employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme which adjusts the bandwidth of a CDR automatically in the background for optimum BER performance by monitoring the phase difference between the incoming data and the recovered clock signal. The proposed CDR supports reference-less all-rate operation and compensates for 20dB of channel loss using a CTLE, a one-tap DFE and a three-tap pre-emphasis filter. The power efficiency of the test chip is 4.88mW/Gb/s.",

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Yoon, JH, Kwon, SW & Bae, HM 2015, A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS. in 2015 IEEE Custom Integrated Circuits Conference, CICC 2015., 7338486, Proceedings of the Custom Integrated Circuits Conference, vol. 2015-November, Institute of Electrical and Electronics Engineers Inc., IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, United States, 28/09/15. https://doi.org/10.1109/CICC.2015.7338486

A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS. / Yoon, Jong Hyeok; Kwon, Soon Won; Bae, Hyeon Min.
2015 IEEE Custom Integrated Circuits Conference, CICC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7338486 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2015-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A DC-to-12.5Gb/s all-rate CDR IC with a single LC VCO is fabricated in 90nm CMOS. Static fractional dividers with an asynchronous phase calibration scheme are employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme which adjusts the bandwidth of a CDR automatically in the background for optimum BER performance by monitoring the phase difference between the incoming data and the recovered clock signal. The proposed CDR supports reference-less all-rate operation and compensates for 20dB of channel loss using a CTLE, a one-tap DFE and a three-tap pre-emphasis filter. The power efficiency of the test chip is 4.88mW/Gb/s.

AB - A DC-to-12.5Gb/s all-rate CDR IC with a single LC VCO is fabricated in 90nm CMOS. Static fractional dividers with an asynchronous phase calibration scheme are employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme which adjusts the bandwidth of a CDR automatically in the background for optimum BER performance by monitoring the phase difference between the incoming data and the recovered clock signal. The proposed CDR supports reference-less all-rate operation and compensates for 20dB of channel loss using a CTLE, a one-tap DFE and a three-tap pre-emphasis filter. The power efficiency of the test chip is 4.88mW/Gb/s.

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A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS

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Keywords

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