A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO-ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition

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Abstract

This paper proposes a 97dB-PSRR, 178.4dB-FOMDR calibration-free 16-channel VCO-ΔΣ ADC system using a PVT-insensitive frequency-locked differential regulation (FLDR) scheme suitable for wireless ExG Acquisition. Thanks to the FLDR, the SNDR degradation in all 16 channels is less than 1dB over 1.4-2V supply and 20-60°C temperature ranges. Implemented in a 0.18μm standard CMOS process, the proposed system consumes 172μW from a 1.4V supply and occupies 2.7mm2 active area, while a single channel consumes 4.2μW and 0.12mm2, respectively.

Original languageEnglish
Title of host publication2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350361469
DOIs
StatePublished - 2024
Event2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 - Honolulu, United States
Duration: 16 Jun 202420 Jun 2024

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Country/TerritoryUnited States
CityHonolulu
Period16/06/2420/06/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

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