A 7.1GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS

Y. H. Park; S. H. Han; J. S. Kim; S. J. Lee; J. H. Kook; J. W. Lim; R. Woo; H. J. Yoo; J. H. Lee; J. H. Lee

A 7.1GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS

Y. H. Park, S. H. Han, J. S. Kim, S. J. Lee, J. H. Kook, J. W. Lim, R. Woo, H. J. Yoo, J. H. Lee, J. H. Lee

Department of Electrical Engineering and Computer Science

Korea Advanced Institute of Science and Technology

Research output: Contribution to journal › Conference article › peer-review

9 Scopus citations

Abstract

A 7.1 GB/s low power three dimensional rendering engine in two dimensional array embedded memory logic (EML) complementary metal oxide semiconductor (CMOS) circuit was proposed. It consists of 8 edge processors (EP), 64 pixel processors (PP), 64 frame buffers (FB) and 64 serial access memories (SAM) on the same chip. The engine was based on the hierarchical octet tree (HOT) structure where commands and data are transferred to the 8 EPs and each EP consists of 8 processing nodes under its control.

Original language	English
Pages (from-to)	242-243
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
State	Published - 2000
Event	2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC - San Francisco, CA, United States Duration: 7 Feb 2000 → 9 Feb 2000

Cite this

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title = "A 7.1GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS",

abstract = "A 7.1 GB/s low power three dimensional rendering engine in two dimensional array embedded memory logic (EML) complementary metal oxide semiconductor (CMOS) circuit was proposed. It consists of 8 edge processors (EP), 64 pixel processors (PP), 64 frame buffers (FB) and 64 serial access memories (SAM) on the same chip. The engine was based on the hierarchical octet tree (HOT) structure where commands and data are transferred to the 8 EPs and each EP consists of 8 processing nodes under its control.",

author = "Park, {Y. H.} and Han, {S. H.} and Kim, {J. S.} and Lee, {S. J.} and Kook, {J. H.} and Lim, {J. W.} and R. Woo and Yoo, {H. J.} and Lee, {J. H.} and Lee, {J. H.}",

year = "2000",

language = "English",

pages = "242--243",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC ; Conference date: 07-02-2000 Through 09-02-2000",

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TY - JOUR

T1 - A 7.1GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS

AU - Park, Y. H.

AU - Han, S. H.

AU - Kim, J. S.

AU - Lee, S. J.

AU - Kook, J. H.

AU - Lim, J. W.

AU - Woo, R.

AU - Yoo, H. J.

AU - Lee, J. H.

PY - 2000

Y1 - 2000

N2 - A 7.1 GB/s low power three dimensional rendering engine in two dimensional array embedded memory logic (EML) complementary metal oxide semiconductor (CMOS) circuit was proposed. It consists of 8 edge processors (EP), 64 pixel processors (PP), 64 frame buffers (FB) and 64 serial access memories (SAM) on the same chip. The engine was based on the hierarchical octet tree (HOT) structure where commands and data are transferred to the 8 EPs and each EP consists of 8 processing nodes under its control.

AB - A 7.1 GB/s low power three dimensional rendering engine in two dimensional array embedded memory logic (EML) complementary metal oxide semiconductor (CMOS) circuit was proposed. It consists of 8 edge processors (EP), 64 pixel processors (PP), 64 frame buffers (FB) and 64 serial access memories (SAM) on the same chip. The engine was based on the hierarchical octet tree (HOT) structure where commands and data are transferred to the 8 EPs and each EP consists of 8 processing nodes under its control.

UR - http://www.scopus.com/inward/record.url?scp=0034428845&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0034428845

SN - 0193-6530

SP - 242

EP - 243

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - 2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC

Y2 - 7 February 2000 through 9 February 2000

ER -

A 7.1GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS

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