A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET

Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel Kossel; Alessandro Cevrero; Ilter Ozkaya; Hyeon Min Bae; Andreas Burg; Thomas Toifl; Yusuf Leblebici

doi:10.1109/A-SSCC47793.2019.9056940

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET

Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel Kossel, Alessandro Cevrero, Ilter Ozkaya, Hyeon Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici

Department of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

This work presents an ADC-based receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols are protected from the channel delay spread by the CP taps. A PAM-4 frame window including CP taps is viewed as a DMT symbol and is equalized similarly to a DMT signal equalization, based on a discrete-time Fourier transform (DFT) and frequency-domain equalizer (FDE). The RX prototype implemented in 14nm FinFET achieves 56Gb/s data-rate at less than 3e-5 pre-FEC BER over a 19dB loss channel at 14GHz dissipating 270mW including the ADC and the DSP data-path excluding the inverse DFT and the BER checker.

Original language	English
Title of host publication	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	239-240
Number of pages	2
ISBN (Electronic)	9781728151069
DOIs	https://doi.org/10.1109/A-SSCC47793.2019.9056940
State	Published - Nov 2019
Event	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China Duration: 4 Nov 2019 → 6 Nov 2019

Publication series

Name	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Conference

Conference	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/Territory	China
City	Macao
Period	4/11/19 → 6/11/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Access to Document

10.1109/A-SSCC47793.2019.9056940

Cite this

Kim, G., Kull, L., Luu, D., Braendli, M., Menolfi, C., Francese, P. A., Yueksel, H., Aprile, C., Morf, T., Kossel, M., Cevrero, A., Ozkaya, I., Bae, H. M., Burg, A., Toifl, T., & Leblebici, Y. (2019). A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 (pp. 239-240). Article 9056940 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC47793.2019.9056940

@inproceedings{0af546d1a4064dc4b6823e03cf019c5a,

title = "A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET",

abstract = "This work presents an ADC-based receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols are protected from the channel delay spread by the CP taps. A PAM-4 frame window including CP taps is viewed as a DMT symbol and is equalized similarly to a DMT signal equalization, based on a discrete-time Fourier transform (DFT) and frequency-domain equalizer (FDE). The RX prototype implemented in 14nm FinFET achieves 56Gb/s data-rate at less than 3e-5 pre-FEC BER over a 19dB loss channel at 14GHz dissipating 270mW including the ADC and the DSP data-path excluding the inverse DFT and the BER checker.",

author = "Gain Kim and Lukas Kull and Danny Luu and Matthias Braendli and Christian Menolfi and Francese, {Pier Andrea} and Hazar Yueksel and Cosimo Aprile and Thomas Morf and Marcel Kossel and Alessandro Cevrero and Ilter Ozkaya and Bae, {Hyeon Min} and Andreas Burg and Thomas Toifl and Yusuf Leblebici",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 ; Conference date: 04-11-2019 Through 06-11-2019",

year = "2019",

month = nov,

doi = "10.1109/A-SSCC47793.2019.9056940",

language = "English",

series = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "239--240",

booktitle = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",

}

Kim, G, Kull, L, Luu, D, Braendli, M, Menolfi, C, Francese, PA, Yueksel, H, Aprile, C, Morf, T, Kossel, M, Cevrero, A, Ozkaya, I, Bae, HM, Burg, A, Toifl, T & Leblebici, Y 2019, A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. in Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019., 9056940, Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Institute of Electrical and Electronics Engineers Inc., pp. 239-240, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macao, China, 4/11/19. https://doi.org/10.1109/A-SSCC47793.2019.9056940

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. / Kim, Gain; Kull, Lukas; Luu, Danny et al.
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 239-240 9056940 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET

AU - Kim, Gain

AU - Kull, Lukas

AU - Luu, Danny

AU - Braendli, Matthias

AU - Menolfi, Christian

AU - Francese, Pier Andrea

AU - Yueksel, Hazar

AU - Aprile, Cosimo

AU - Morf, Thomas

AU - Kossel, Marcel

AU - Cevrero, Alessandro

AU - Ozkaya, Ilter

AU - Bae, Hyeon Min

AU - Burg, Andreas

AU - Toifl, Thomas

AU - Leblebici, Yusuf

PY - 2019/11

Y1 - 2019/11

N2 - This work presents an ADC-based receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols are protected from the channel delay spread by the CP taps. A PAM-4 frame window including CP taps is viewed as a DMT symbol and is equalized similarly to a DMT signal equalization, based on a discrete-time Fourier transform (DFT) and frequency-domain equalizer (FDE). The RX prototype implemented in 14nm FinFET achieves 56Gb/s data-rate at less than 3e-5 pre-FEC BER over a 19dB loss channel at 14GHz dissipating 270mW including the ADC and the DSP data-path excluding the inverse DFT and the BER checker.

AB - This work presents an ADC-based receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols are protected from the channel delay spread by the CP taps. A PAM-4 frame window including CP taps is viewed as a DMT symbol and is equalized similarly to a DMT signal equalization, based on a discrete-time Fourier transform (DFT) and frequency-domain equalizer (FDE). The RX prototype implemented in 14nm FinFET achieves 56Gb/s data-rate at less than 3e-5 pre-FEC BER over a 19dB loss channel at 14GHz dissipating 270mW including the ADC and the DSP data-path excluding the inverse DFT and the BER checker.

UR - http://www.scopus.com/inward/record.url?scp=85083678954&partnerID=8YFLogxK

U2 - 10.1109/A-SSCC47793.2019.9056940

DO - 10.1109/A-SSCC47793.2019.9056940

M3 - Conference contribution

AN - SCOPUS:85083678954

T3 - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

SP - 239

EP - 240

BT - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Y2 - 4 November 2019 through 6 November 2019

ER -

Kim G, Kull L, Luu D, Braendli M, Menolfi C, Francese PA et al. A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 239-240. 9056940. (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). doi: 10.1109/A-SSCC47793.2019.9056940

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET

Abstract

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