TY - GEN
T1 - A 480-MHz to 1-GHz sub-picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13-μm CMOS
AU - Lee, Joonhee
AU - Kim, Kyunglok
AU - Lee, Junghyup
AU - Jang, Taekwang
AU - Cho, Seonghwan
PY - 2007
Y1 - 2007
N2 - In this paper, an ultra-low jitter clock generator that employs a novel automatic frequency calibration (AFC) technique is presented. To achieve low jitter, the clock generator uses an LC-VCO with 5-bit switched tuning scheme. The clock output is taken from the output of a multi-modulus divider, which increases the output frequency range with small variation in the loop bandwidth. The capacitor array of the the VCO is controlled by a novel AFC technique that performs binary search for fast calibration and fine search to select an optimum tuning curve. A prototype chip implemented in 0.13-μm CMOS process achieves 480 MHz to 1 GHz of output frequency while consuming 22 mW from a 1.2 V supply. The measured rms jitter and calibration time of the proposed clock generator are 940 fs at 600 MHz and 350 ns, respectively. These numbers are the fastest calibration time and one of the lowest jitter that have been reported in a clock generator.
AB - In this paper, an ultra-low jitter clock generator that employs a novel automatic frequency calibration (AFC) technique is presented. To achieve low jitter, the clock generator uses an LC-VCO with 5-bit switched tuning scheme. The clock output is taken from the output of a multi-modulus divider, which increases the output frequency range with small variation in the loop bandwidth. The capacitor array of the the VCO is controlled by a novel AFC technique that performs binary search for fast calibration and fine search to select an optimum tuning curve. A prototype chip implemented in 0.13-μm CMOS process achieves 480 MHz to 1 GHz of output frequency while consuming 22 mW from a 1.2 V supply. The measured rms jitter and calibration time of the proposed clock generator are 940 fs at 600 MHz and 350 ns, respectively. These numbers are the fastest calibration time and one of the lowest jitter that have been reported in a clock generator.
UR - http://www.scopus.com/inward/record.url?scp=51349127672&partnerID=8YFLogxK
U2 - 10.1109/ASSCC.2007.4425733
DO - 10.1109/ASSCC.2007.4425733
M3 - Conference contribution
AN - SCOPUS:51349127672
SN - 1424413605
SN - 9781424413607
T3 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
SP - 67
EP - 70
BT - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
T2 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Y2 - 12 November 2007 through 14 November 2007
ER -