A 480-MHz to 1-GHz sub-picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13-μm CMOS

Joonhee Lee, Kyunglok Kim, Junghyup Lee, Taekwang Jang, Seonghwan Cho

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

24 Scopus citations

Abstract

In this paper, an ultra-low jitter clock generator that employs a novel automatic frequency calibration (AFC) technique is presented. To achieve low jitter, the clock generator uses an LC-VCO with 5-bit switched tuning scheme. The clock output is taken from the output of a multi-modulus divider, which increases the output frequency range with small variation in the loop bandwidth. The capacitor array of the the VCO is controlled by a novel AFC technique that performs binary search for fast calibration and fine search to select an optimum tuning curve. A prototype chip implemented in 0.13-μm CMOS process achieves 480 MHz to 1 GHz of output frequency while consuming 22 mW from a 1.2 V supply. The measured rms jitter and calibration time of the proposed clock generator are 940 fs at 600 MHz and 350 ns, respectively. These numbers are the fastest calibration time and one of the lowest jitter that have been reported in a clock generator.

Original languageEnglish
Title of host publication2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages67-70
Number of pages4
DOIs
StatePublished - 2007
Event2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of
Duration: 12 Nov 200714 Nov 2007

Publication series

Name2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Conference

Conference2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country/TerritoryKorea, Republic of
CityJeju
Period12/11/0714/11/07

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