A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs

Junghyup Lee; Pyoungwon Park; Seonghwan Cho; Minkyu Je

doi:10.1109/ISSCC.2015.7062948

A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs

Junghyup Lee, Pyoungwon Park, Seonghwan Cho, Minkyu Je

Department of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

26 Scopus citations

Abstract

Low-power CMOS reference clock oscillators have been widely used in miniaturized SoCs for emerging microsystems such as implantable biomedical devices and smart sensors [1-3]. In such SoCs, as the supply voltage shrinks and the level of analog and digital circuit integration increases to meet rigorous power and area constraints, the noise from other blocks (especially digital blocks) couples through supply and ground lines and poses a serious threat to the performance of CMOS reference clock oscillators.

Original language	English
Title of host publication	2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	106-107
Number of pages	2
ISBN (Electronic)	9781479962235
DOIs	https://doi.org/10.1109/ISSCC.2015.7062948
State	Published - 17 Mar 2015
Event	2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States Duration: 22 Feb 2015 → 26 Feb 2015

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	58
ISSN (Print)	0193-6530

Conference

Conference	2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
Country/Territory	United States
City	San Francisco
Period	22/02/15 → 26/02/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

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10.1109/ISSCC.2015.7062948

Cite this

Lee, J., Park, P., Cho, S., & Je, M. (2015). A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers (pp. 106-107). Article 7062948 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 58). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2015.7062948

Lee, Junghyup ; Park, Pyoungwon ; Cho, Seonghwan et al. / A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 106-107 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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abstract = "Low-power CMOS reference clock oscillators have been widely used in miniaturized SoCs for emerging microsystems such as implantable biomedical devices and smart sensors [1-3]. In such SoCs, as the supply voltage shrinks and the level of analog and digital circuit integration increases to meet rigorous power and area constraints, the noise from other blocks (especially digital blocks) couples through supply and ground lines and poses a serious threat to the performance of CMOS reference clock oscillators.",

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Lee, J, Park, P, Cho, S & Je, M 2015, A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. in 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers., 7062948, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 58, Institute of Electrical and Electronics Engineers Inc., pp. 106-107, 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers, San Francisco, United States, 22/02/15. https://doi.org/10.1109/ISSCC.2015.7062948

A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. / Lee, Junghyup; Park, Pyoungwon; Cho, Seonghwan et al.
2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. 106-107 7062948 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 58).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Lee J, Park P, Cho S, Je M. A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. 106-107. 7062948. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2015.7062948

A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs

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