A 4 × 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS

Joon Yeong Lee; Jaehyeok Yang; Jong Hyeok Yoon; Soon Won Kwon; Hyosup Won; Jinho Han; Hyeon Min Bae

doi:10.1109/TVLSI.2015.2502957

A 4 × 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS

Joon Yeong Lee
, Jaehyeok Yang
, Jong Hyeok Yoon
, Soon Won Kwon
, Hyosup Won
, Jinho Han
, Hyeon Min Bae

Department of Electrical Engineering and Computer Science

Korea Advanced Institute of Science and Technology

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

A four-parallel 10-Gb/s referenceless-and-masterless phase rotator-based transceiver is presented. Entire lanes operate independently just like the conventional voltage-controlled-oscillator-based parallel referenceless designs while saving power and area. The measured recovered-clock jitter in each lane is 1.24 ps_rms and the transceiver surpasses the OC-192 jitter-tolerance specification. The power efficiency of the proposed parallel transceiver fabricated in a 90-nm CMOS process is 6.325 mW/(Gb/s).

Original language	English
Article number	7350153
Pages (from-to)	2310-2320
Number of pages	11
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	24
Issue number	6
DOIs	https://doi.org/10.1109/TVLSI.2015.2502957
State	Published - Jun 2016

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

Clock and data recovery (CDR)
Stochastic reference clock generator (SRCG)
frequency-locked loop (FLL)
masterless
parallel transceiver
phase-locked loop (PLL)
referenceless

Access to Document

10.1109/TVLSI.2015.2502957

Cite this

@article{b8ae0caec33f474b85fba839ef452aae,

title = "A 4 × 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS",

abstract = "A four-parallel 10-Gb/s referenceless-and-masterless phase rotator-based transceiver is presented. Entire lanes operate independently just like the conventional voltage-controlled-oscillator-based parallel referenceless designs while saving power and area. The measured recovered-clock jitter in each lane is 1.24 psrms and the transceiver surpasses the OC-192 jitter-tolerance specification. The power efficiency of the proposed parallel transceiver fabricated in a 90-nm CMOS process is 6.325 mW/(Gb/s).",

keywords = "Clock and data recovery (CDR), Stochastic reference clock generator (SRCG), frequency-locked loop (FLL), masterless, parallel transceiver, phase-locked loop (PLL), referenceless",

author = "Lee, \{Joon Yeong\} and Jaehyeok Yang and Yoon, \{Jong Hyeok\} and Kwon, \{Soon Won\} and Hyosup Won and Jinho Han and Bae, \{Hyeon Min\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.",

year = "2016",

month = jun,

doi = "10.1109/TVLSI.2015.2502957",

language = "English",

volume = "24",

pages = "2310--2320",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - A 4 × 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS

AU - Lee, Joon Yeong

AU - Yang, Jaehyeok

AU - Yoon, Jong Hyeok

AU - Kwon, Soon Won

AU - Won, Hyosup

AU - Han, Jinho

AU - Bae, Hyeon Min

PY - 2016/6

Y1 - 2016/6

N2 - A four-parallel 10-Gb/s referenceless-and-masterless phase rotator-based transceiver is presented. Entire lanes operate independently just like the conventional voltage-controlled-oscillator-based parallel referenceless designs while saving power and area. The measured recovered-clock jitter in each lane is 1.24 psrms and the transceiver surpasses the OC-192 jitter-tolerance specification. The power efficiency of the proposed parallel transceiver fabricated in a 90-nm CMOS process is 6.325 mW/(Gb/s).

AB - A four-parallel 10-Gb/s referenceless-and-masterless phase rotator-based transceiver is presented. Entire lanes operate independently just like the conventional voltage-controlled-oscillator-based parallel referenceless designs while saving power and area. The measured recovered-clock jitter in each lane is 1.24 psrms and the transceiver surpasses the OC-192 jitter-tolerance specification. The power efficiency of the proposed parallel transceiver fabricated in a 90-nm CMOS process is 6.325 mW/(Gb/s).

KW - Clock and data recovery (CDR)

KW - Stochastic reference clock generator (SRCG)

KW - frequency-locked loop (FLL)

KW - masterless

KW - parallel transceiver

KW - phase-locked loop (PLL)

KW - referenceless

UR - https://www.scopus.com/pages/publications/84949895235

U2 - 10.1109/TVLSI.2015.2502957

DO - 10.1109/TVLSI.2015.2502957

M3 - Article

AN - SCOPUS:84949895235

SN - 1063-8210

VL - 24

SP - 2310

EP - 2320

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 6

M1 - 7350153

ER -

A 4 × 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS

Abstract

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this