Abstract
This paper presents a 3.125 Gb/s to 28.125 Gb/s multi-standard channel-independent parallel transceiver. The proposed clock and data recovery (CDR) IC achieves wide tuning range with low clock jitter because a ring oscillator in each channel is injection-locked to an LC VCO in a global clock generator. Each CDR lane generates a channel-independent injection clock signal using a variable clock divider and a highly linear phase rotator. In addition, a frequency tracking loop using a natural frequency detector is proposed to align the frequency of an injection-locked oscillator to the input data rate to suppress a periodic spur under injection. The test chip fabricated in 40nm CMOS achieves a power efficiency of 4.72 mW/Gb/s while generating integrated jitter of 976 psrms.
| Original language | English |
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| Title of host publication | 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1-4 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781538624838 |
| DOIs | |
| State | Published - 9 May 2018 |
| Event | 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 - San Diego, United States Duration: 8 Apr 2018 → 11 Apr 2018 |
Publication series
| Name | 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 |
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Conference
| Conference | 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 |
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| Country/Territory | United States |
| City | San Diego |
| Period | 8/04/18 → 11/04/18 |
Bibliographical note
Publisher Copyright:© 2018 IEEE.
Keywords
- Clock and data recovery
- channel-independent operation
- frequency tracking loop
- harmonic distortion compensator
- injection-locked loop
- multi-standard transceiver
- natural frequency detector