A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform

Jaewon Lee; Seoyoung Jang; Yujin Choi; Donggeon Kim; Matthias Braendli; Thomas Morf; Marcel Kossel; Pier Andrea Francese; Gain Kim

doi:10.1109/TVLSI.2025.3553400

A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform

Jaewon Lee, Seoyoung Jang, Yujin Choi, Donggeon Kim, Matthias Braendli, Thomas Morf, Marcel Kossel, Pier Andrea Francese, Gain Kim

Department of Electrical Engineering and Computer Science

Research output: Contribution to journal › Article › peer-review

Abstract

This article presents a 2-lane 2 x 2 multiple-input, multiple-output (MIMO) 4-level pulse amplitude modulation (PAM-4) minimum mean-squared-error (MMSE)-decision-feedback equalizer (DFE) with far-end crosstalk (FEXT) cancellation for digital-to-analog converter (DAC)-/analog-to-digital converter (ADC)-based high-speed serial links. The receiver (RX) datapath is designed with a 15-tap MIMO feedforward equalizer (FFE) and a one-tap MIMO DFE with the least mean square (LMS), enabling adaptation to channel variation while maintaining the MMSE setting. The RX digital signal processor (DSP) place and route (PnR) in a 28-nm CMOS is estimated to consume 201 mW/lane at a 56-Gb/s/lane data rate while occupying a 0.5-mm²/lane silicon area. We further implement a real-time evaluation platform to verify the functionality of the MIMO PAM-4 MMSE-DFE with rapid bit-error-rate (BER) testing on RFSoC. The measurement result demonstrates that the MIMO MMSE-DFE significantly improves BER performance from 2.75e⁻³ to 1.31e⁻⁷ compared with equalization without FEXT cancellation when communicating over a channel exhibiting 12.4-dB insertion loss (IL) and 13.2-dB IL-to-crosstalk ratio (ICR) at Nyquist.

Original language	English
Pages (from-to)	1570-1581
Number of pages	12
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	33
Issue number	6
DOIs	https://doi.org/10.1109/TVLSI.2025.3553400
State	Published - 2025

Bibliographical note

Publisher Copyright:
© 1993-2012 IEEE.

Keywords

Decision-feedback equalizer (DFE)
RFSoC
far-end crosstalk (FEXT)
field-programmable gate array (FPGA)
minimum mean-squared error (MMSE)
multiple-input
multiple-output (MIMO)
pulse amplitude modulation
serial link
wireline transceiver (TRX)

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10.1109/TVLSI.2025.3553400

Cite this

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title = "A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform",

abstract = "This article presents a 2-lane 2 x 2 multiple-input, multiple-output (MIMO) 4-level pulse amplitude modulation (PAM-4) minimum mean-squared-error (MMSE)-decision-feedback equalizer (DFE) with far-end crosstalk (FEXT) cancellation for digital-to-analog converter (DAC)-/analog-to-digital converter (ADC)-based high-speed serial links. The receiver (RX) datapath is designed with a 15-tap MIMO feedforward equalizer (FFE) and a one-tap MIMO DFE with the least mean square (LMS), enabling adaptation to channel variation while maintaining the MMSE setting. The RX digital signal processor (DSP) place and route (PnR) in a 28-nm CMOS is estimated to consume 201 mW/lane at a 56-Gb/s/lane data rate while occupying a 0.5-mm2/lane silicon area. We further implement a real-time evaluation platform to verify the functionality of the MIMO PAM-4 MMSE-DFE with rapid bit-error-rate (BER) testing on RFSoC. The measurement result demonstrates that the MIMO MMSE-DFE significantly improves BER performance from 2.75e−3 to 1.31e−7 compared with equalization without FEXT cancellation when communicating over a channel exhibiting 12.4-dB insertion loss (IL) and 13.2-dB IL-to-crosstalk ratio (ICR) at Nyquist.",

keywords = "Decision-feedback equalizer (DFE), RFSoC, far-end crosstalk (FEXT), field-programmable gate array (FPGA), minimum mean-squared error (MMSE), multiple-input, multiple-output (MIMO), pulse amplitude modulation, serial link, wireline transceiver (TRX)",

author = "Jaewon Lee and Seoyoung Jang and Yujin Choi and Donggeon Kim and Matthias Braendli and Thomas Morf and Marcel Kossel and Francese, {Pier Andrea} and Gain Kim",

note = "Publisher Copyright: {\textcopyright} 1993-2012 IEEE.",

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doi = "10.1109/TVLSI.2025.3553400",

language = "English",

volume = "33",

pages = "1570--1581",

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T1 - A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform

AU - Lee, Jaewon

AU - Jang, Seoyoung

AU - Choi, Yujin

AU - Kim, Donggeon

AU - Braendli, Matthias

AU - Morf, Thomas

AU - Kossel, Marcel

AU - Francese, Pier Andrea

AU - Kim, Gain

PY - 2025

Y1 - 2025

N2 - This article presents a 2-lane 2 x 2 multiple-input, multiple-output (MIMO) 4-level pulse amplitude modulation (PAM-4) minimum mean-squared-error (MMSE)-decision-feedback equalizer (DFE) with far-end crosstalk (FEXT) cancellation for digital-to-analog converter (DAC)-/analog-to-digital converter (ADC)-based high-speed serial links. The receiver (RX) datapath is designed with a 15-tap MIMO feedforward equalizer (FFE) and a one-tap MIMO DFE with the least mean square (LMS), enabling adaptation to channel variation while maintaining the MMSE setting. The RX digital signal processor (DSP) place and route (PnR) in a 28-nm CMOS is estimated to consume 201 mW/lane at a 56-Gb/s/lane data rate while occupying a 0.5-mm2/lane silicon area. We further implement a real-time evaluation platform to verify the functionality of the MIMO PAM-4 MMSE-DFE with rapid bit-error-rate (BER) testing on RFSoC. The measurement result demonstrates that the MIMO MMSE-DFE significantly improves BER performance from 2.75e−3 to 1.31e−7 compared with equalization without FEXT cancellation when communicating over a channel exhibiting 12.4-dB insertion loss (IL) and 13.2-dB IL-to-crosstalk ratio (ICR) at Nyquist.

AB - This article presents a 2-lane 2 x 2 multiple-input, multiple-output (MIMO) 4-level pulse amplitude modulation (PAM-4) minimum mean-squared-error (MMSE)-decision-feedback equalizer (DFE) with far-end crosstalk (FEXT) cancellation for digital-to-analog converter (DAC)-/analog-to-digital converter (ADC)-based high-speed serial links. The receiver (RX) datapath is designed with a 15-tap MIMO feedforward equalizer (FFE) and a one-tap MIMO DFE with the least mean square (LMS), enabling adaptation to channel variation while maintaining the MMSE setting. The RX digital signal processor (DSP) place and route (PnR) in a 28-nm CMOS is estimated to consume 201 mW/lane at a 56-Gb/s/lane data rate while occupying a 0.5-mm2/lane silicon area. We further implement a real-time evaluation platform to verify the functionality of the MIMO PAM-4 MMSE-DFE with rapid bit-error-rate (BER) testing on RFSoC. The measurement result demonstrates that the MIMO MMSE-DFE significantly improves BER performance from 2.75e−3 to 1.31e−7 compared with equalization without FEXT cancellation when communicating over a channel exhibiting 12.4-dB insertion loss (IL) and 13.2-dB IL-to-crosstalk ratio (ICR) at Nyquist.

KW - Decision-feedback equalizer (DFE)

KW - RFSoC

KW - far-end crosstalk (FEXT)

KW - field-programmable gate array (FPGA)

KW - minimum mean-squared error (MMSE)

KW - multiple-input

KW - multiple-output (MIMO)

KW - pulse amplitude modulation

KW - serial link

KW - wireline transceiver (TRX)

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U2 - 10.1109/TVLSI.2025.3553400

DO - 10.1109/TVLSI.2025.3553400

M3 - Article

AN - SCOPUS:105002382492

SN - 1063-8210

VL - 33

SP - 1570

EP - 1581

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 6

ER -

A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform

Abstract

Bibliographical note

Keywords

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