A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Gain Kim; Marcel Kossel; Alessandro Cevrero; Ilter Ozkaya; Andreas Burg; Thomas Toifl; Yusuf Leblebici; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf

doi:10.1109/JSSC.2019.2938414

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Gain Kim
, Marcel Kossel
, Alessandro Cevrero
, Ilter Ozkaya
, Andreas Burg
, Thomas Toifl
, Yusuf Leblebici
, Lukas Kull
, Danny Luu
, Matthias Braendli
, Christian Menolfi
, Pier Andrea Francese
, Hazar Yueksel
, Cosimo Aprile
, Thomas Morf

Department of Electrical Engineering and Computer Science

Research output: Contribution to journal › Article › peer-review

49 Scopus citations

Abstract

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed and routed digital signal processor (DSP) following a 10-bit time-interleaved pipelined successive-approximation register analog-to-digital converter (TI-PISAR ADC). The prototype RX chip implemented in a 14-nm FinFET process demonstrates a lane data rate of 56 Gb/s dissipating 161 mW including the ADC and the DSP power. The energy efficiency of 1.2 pJ/b for the DSP and 2.9 pJ/b for the entire RX was achieved with the data-rate of 56 Gb/s for communicating over channels exhibiting up to 28-dB loss at 14 GHz with a bit-error-rate (BER) better than 2e-4.

Original language	English
Article number	8846586
Pages (from-to)	38-48
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	55
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2019.2938414
State	Published - Jan 2020

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

Keywords

Discrete multi-tone (DMT)
SerDes
inter-symbol interference (ISI)
orthogonal frequency-division multiplexing (OFDM)
receiver
serial-data transceiver
wireline

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/JSSC.2019.2938414

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Kim, G., Kossel, M., Cevrero, A., Ozkaya, I., Burg, A., Toifl, T., Leblebici, Y., Kull, L., Luu, D., Braendli, M., Menolfi, C., Francese, P. A., Yueksel, H., Aprile, C., & Morf, T. (2020). A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE Journal of Solid-State Circuits, 55(1), 38-48. Article 8846586. https://doi.org/10.1109/JSSC.2019.2938414

@article{4e94997efd3d46f7b08a4713271779f4,

title = "A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET",

abstract = "This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed and routed digital signal processor (DSP) following a 10-bit time-interleaved pipelined successive-approximation register analog-to-digital converter (TI-PISAR ADC). The prototype RX chip implemented in a 14-nm FinFET process demonstrates a lane data rate of 56 Gb/s dissipating 161 mW including the ADC and the DSP power. The energy efficiency of 1.2 pJ/b for the DSP and 2.9 pJ/b for the entire RX was achieved with the data-rate of 56 Gb/s for communicating over channels exhibiting up to 28-dB loss at 14 GHz with a bit-error-rate (BER) better than 2e-4.",

keywords = "Discrete multi-tone (DMT), SerDes, inter-symbol interference (ISI), orthogonal frequency-division multiplexing (OFDM), receiver, serial-data transceiver, wireline",

author = "Gain Kim and Marcel Kossel and Alessandro Cevrero and Ilter Ozkaya and Andreas Burg and Thomas Toifl and Yusuf Leblebici and Lukas Kull and Danny Luu and Matthias Braendli and Christian Menolfi and Francese, \{Pier Andrea\} and Hazar Yueksel and Cosimo Aprile and Thomas Morf",

note = "Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

year = "2020",

month = jan,

doi = "10.1109/JSSC.2019.2938414",

language = "English",

volume = "55",

pages = "38--48",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

Kim, G, Kossel, M, Cevrero, A, Ozkaya, I, Burg, A, Toifl, T, Leblebici, Y, Kull, L, Luu, D, Braendli, M, Menolfi, C, Francese, PA, Yueksel, H, Aprile, C & Morf, T 2020, 'A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET', IEEE Journal of Solid-State Circuits, vol. 55, no. 1, 8846586, pp. 38-48. https://doi.org/10.1109/JSSC.2019.2938414

TY - JOUR

T1 - A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

AU - Kim, Gain

AU - Kossel, Marcel

AU - Cevrero, Alessandro

AU - Ozkaya, Ilter

AU - Burg, Andreas

AU - Toifl, Thomas

AU - Leblebici, Yusuf

AU - Kull, Lukas

AU - Luu, Danny

AU - Braendli, Matthias

AU - Menolfi, Christian

AU - Francese, Pier Andrea

AU - Yueksel, Hazar

AU - Aprile, Cosimo

AU - Morf, Thomas

PY - 2020/1

Y1 - 2020/1

N2 - This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed and routed digital signal processor (DSP) following a 10-bit time-interleaved pipelined successive-approximation register analog-to-digital converter (TI-PISAR ADC). The prototype RX chip implemented in a 14-nm FinFET process demonstrates a lane data rate of 56 Gb/s dissipating 161 mW including the ADC and the DSP power. The energy efficiency of 1.2 pJ/b for the DSP and 2.9 pJ/b for the entire RX was achieved with the data-rate of 56 Gb/s for communicating over channels exhibiting up to 28-dB loss at 14 GHz with a bit-error-rate (BER) better than 2e-4.

AB - This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed and routed digital signal processor (DSP) following a 10-bit time-interleaved pipelined successive-approximation register analog-to-digital converter (TI-PISAR ADC). The prototype RX chip implemented in a 14-nm FinFET process demonstrates a lane data rate of 56 Gb/s dissipating 161 mW including the ADC and the DSP power. The energy efficiency of 1.2 pJ/b for the DSP and 2.9 pJ/b for the entire RX was achieved with the data-rate of 56 Gb/s for communicating over channels exhibiting up to 28-dB loss at 14 GHz with a bit-error-rate (BER) better than 2e-4.

KW - Discrete multi-tone (DMT)

KW - SerDes

KW - inter-symbol interference (ISI)

KW - orthogonal frequency-division multiplexing (OFDM)

KW - receiver

KW - serial-data transceiver

KW - wireline

UR - https://www.scopus.com/pages/publications/85077796591

U2 - 10.1109/JSSC.2019.2938414

DO - 10.1109/JSSC.2019.2938414

M3 - Article

AN - SCOPUS:85077796591

SN - 0018-9200

VL - 55

SP - 38

EP - 48

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 1

M1 - 8846586

ER -

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Abstract

Bibliographical note

Keywords

UN SDGs

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