A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation

Minyoung Song; Sunghoon Ahn; Inhwa Jung; Yongtae Kim; Chulwoo Kim

doi:10.1109/CICC.2008.4672119

A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation

Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim

Department of Electrical Engineering and Computer Science

Korea University

Research output: Contribution to journal › Conference article › peer-review

10 Scopus citations

Abstract

A spread spectrum clock generator is implemented in a 0.18μm CMOS process employing the proposed piecewise linear modulation profile to significantly reduce EMI with a simple implementation. A high resolution fractional divider to reduce quantization noise from the modulation is proposed as well. A peak power reduction level of 14.2dB with 5000ppm down spreading and 27.88ps_pp of jitter in the SSCG without modulation are measured.

Original language	English
Article number	4672119
Pages (from-to)	455-458
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672119
State	Published - 2008
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: 21 Sep 2008 → 24 Sep 2008

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10.1109/CICC.2008.4672119

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abstract = "A spread spectrum clock generator is implemented in a 0.18μm CMOS process employing the proposed piecewise linear modulation profile to significantly reduce EMI with a simple implementation. A high resolution fractional divider to reduce quantization noise from the modulation is proposed as well. A peak power reduction level of 14.2dB with 5000ppm down spreading and 27.88pspp of jitter in the SSCG without modulation are measured.",

author = "Minyoung Song and Sunghoon Ahn and Inhwa Jung and Yongtae Kim and Chulwoo Kim",

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AU - Kim, Yongtae

AU - Kim, Chulwoo

PY - 2008

Y1 - 2008

N2 - A spread spectrum clock generator is implemented in a 0.18μm CMOS process employing the proposed piecewise linear modulation profile to significantly reduce EMI with a simple implementation. A high resolution fractional divider to reduce quantization noise from the modulation is proposed as well. A peak power reduction level of 14.2dB with 5000ppm down spreading and 27.88pspp of jitter in the SSCG without modulation are measured.

AB - A spread spectrum clock generator is implemented in a 0.18μm CMOS process employing the proposed piecewise linear modulation profile to significantly reduce EMI with a simple implementation. A high resolution fractional divider to reduce quantization noise from the modulation is proposed as well. A peak power reduction level of 14.2dB with 5000ppm down spreading and 27.88pspp of jitter in the SSCG without modulation are measured.

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DO - 10.1109/CICC.2008.4672119

M3 - Conference article

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SN - 0886-5930

SP - 455

EP - 458

JO - Proceedings of the Custom Integrated Circuits Conference

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T2 - IEEE 2008 Custom Integrated Circuits Conference, CICC 2008

Y2 - 21 September 2008 through 24 September 2008

ER -

A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation

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