TY - GEN
T1 - A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC
AU - Song, Minyoung
AU - Kwak, Young Ho
AU - Ahn, Sunghoon
AU - Kim, Wooseok
AU - Park, Byeong Ha
AU - Kim, Chulwoo
PY - 2009
Y1 - 2009
N2 - An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65nm CMOS process burns 17mW and occupies 0.4mm2. The measured jitters are 1.1nspp and 223.6ps rms, respectively with a multiplication factor of 1,024.
AB - An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65nm CMOS process burns 17mW and occupies 0.4mm2. The measured jitters are 1.1nspp and 223.6ps rms, respectively with a multiplication factor of 1,024.
UR - http://www.scopus.com/inward/record.url?scp=74049090860&partnerID=8YFLogxK
U2 - 10.1109/CICC.2009.5280849
DO - 10.1109/CICC.2009.5280849
M3 - Conference contribution
AN - SCOPUS:74049090860
SN - 9781424440726
T3 - Proceedings of the Custom Integrated Circuits Conference
SP - 243
EP - 246
BT - 2009 IEEE Custom Integrated Circuits Conference, CICC '09
T2 - 2009 IEEE Custom Integrated Circuits Conference, CICC '09
Y2 - 13 September 2009 through 16 September 2009
ER -