A 10-Gb/s CDR with an adaptive optimum loop-bandwidth calibrator for serial communication links

Joon Yeong Lee; Jong Hyeok Yoon; Hyeon Min Bae

doi:10.1109/TCSI.2014.2309861

A 10-Gb/s CDR with an adaptive optimum loop-bandwidth calibrator for serial communication links

Joon Yeong Lee, Jong Hyeok Yoon, Hyeon Min Bae

Department of Electrical Engineering and Computer Science

Korea Advanced Institute of Science and Technology

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 μm CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10^-13 while consuming 82 mW at 10-Gb/s.

Original language	English
Article number	6780981
Pages (from-to)	2466-2472
Number of pages	7
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	61
Issue number	8
DOIs	https://doi.org/10.1109/TCSI.2014.2309861
State	Published - Aug 2014

Keywords

Bang-bang PLL
CDR
Kalman gain
serial links
serial-in/serial-out

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10.1109/TCSI.2014.2309861

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title = "A 10-Gb/s CDR with an adaptive optimum loop-bandwidth calibrator for serial communication links",

abstract = "This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 μm CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10-13 while consuming 82 mW at 10-Gb/s.",

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AB - This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 μm CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10-13 while consuming 82 mW at 10-Gb/s.

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A 10-Gb/s CDR with an adaptive optimum loop-bandwidth calibrator for serial communication links

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Keywords

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