A 0.9pJ/Cycle 8ppm/°C DFLL-Based Wakeup Timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing

Ming Ding, Minyoung Song, Evgenii Tiurin, Stefano Traferro, Yao Hong Liu, Christian Bachmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

An on-chip DFLL (Digitally Frequency Locked Loop) based wakeup timer with a time-domain trimming featuring an embedded temperature sensor is presented. The proposed trimming exploits the deterministic temperature characteristics of two complementary resistors and results in a fine trimming step (±1ppm), allowing a small frequency error after trimming (<±20ppm). The temperature sensing is running in the background with negligible power (2%) and hardware overhead (<1%). The chip is fabricated in 40nm CMOS, consumes 380nW, resulting 0.9pJ/cycle energy efficiency while achieving 8ppm/°C from -40°C to 80°C.

Original languageEnglish
Title of host publication2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728199429
DOIs
StatePublished - Jun 2020
Event2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, United States
Duration: 16 Jun 202019 Jun 2020

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2020-June

Conference

Conference2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
Country/TerritoryUnited States
CityHonolulu
Period16/06/2019/06/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

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