A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology

A time-to-digital converter (TDC) is a key element for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of quantization. Vernier delay-line-based TDCs [1] are a good example. Their performance, however, is limited by delay variation and random mismatch among delay cells, unless additional error correction or external control are applied. A time-domain successive-approximation scheme [2] could be an option to achieve high resolution but it consumes too much power and area to generate precisely tuned delay cells. In another case, time-amplifier-based multi-step TDCs [3,4] that can alleviate the requirement on the minimum unit delay of the quantization by time-difference amplification, may be an attractive option. However these tend to be power-hungry or to require additional calibration circuitries due to the inaccuracy and PVT vulnerability of the time amplifier or time register. In this paper, we present a simple, low-power, and PVT-variation-tolerant TDC architecture without any calibration, using stochastic phase interpolation and 16x spatial redundancy.