30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel Kossel; Alessandro Cevrero; Ilter Ozkaya; Andreas Burg; Thomas Toifl; Yusuf Leblebici

doi:10.1109/ISSCC.2019.8662505

30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel Kossel, Alessandro Cevrero, Ilter Ozkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici

Department of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

16 Scopus citations

Abstract

The increasing demand on bandwidth for communicating among processors through wired interconnects in large-scale servers motivates the increase in the lane-data-rate from the current 28Gb/s to 56Gb/s or further. Recently published works [1]-[3] demonstrated ADC-based receiver (RX) prototypes equalizing > 56 Gb/s PAM-4 symbols for legacy channels with pre-FEC BERs of less than 2E-4 satisfying IEEE p802.bj/bs pre-FEC BER requirements. While the ADC-based > 56 Gb/s PAM-4 RXs provide strong equalization performance using a large number of feed-forward equalization (FFE) taps and a few decision-feedback equalization (DFE) taps [1], [2] implemented in digital, their power consumption remains excessive due to heavy arithmetic operations in the DSP.

Original language	English
Title of host publication	2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	476-478
Number of pages	3
ISBN (Electronic)	9781538685310
DOIs	https://doi.org/10.1109/ISSCC.2019.8662505
State	Published - 6 Mar 2019
Event	2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 - San Francisco, United States Duration: 17 Feb 2019 → 21 Feb 2019

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	2019-February
ISSN (Print)	0193-6530

Conference

Conference	2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
Country/Territory	United States
City	San Francisco
Period	17/02/19 → 21/02/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

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10.1109/ISSCC.2019.8662505

Cite this

Kim, G., Kull, L., Luu, D., Braendli, M., Menolfi, C., Francese, P. A., Yueksel, H., Aprile, C., Morf, T., Kossel, M., Cevrero, A., Ozkaya, I., Burg, A., Toifl, T., & Leblebici, Y. (2019). 30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. In 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 (pp. 476-478). Article 8662505 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2019-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2019.8662505

@inproceedings{01ef1f39fadf42e5ab6df290e09dc86c,

title = "30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET",

abstract = "The increasing demand on bandwidth for communicating among processors through wired interconnects in large-scale servers motivates the increase in the lane-data-rate from the current 28Gb/s to 56Gb/s or further. Recently published works [1]-[3] demonstrated ADC-based receiver (RX) prototypes equalizing > 56 Gb/s PAM-4 symbols for legacy channels with pre-FEC BERs of less than 2E-4 satisfying IEEE p802.bj/bs pre-FEC BER requirements. While the ADC-based > 56 Gb/s PAM-4 RXs provide strong equalization performance using a large number of feed-forward equalization (FFE) taps and a few decision-feedback equalization (DFE) taps [1], [2] implemented in digital, their power consumption remains excessive due to heavy arithmetic operations in the DSP.",

author = "Gain Kim and Lukas Kull and Danny Luu and Matthias Braendli and Christian Menolfi and Francese, \{Pier Andrea\} and Hazar Yueksel and Cosimo Aprile and Thomas Morf and Marcel Kossel and Alessandro Cevrero and Ilter Ozkaya and Andreas Burg and Thomas Toifl and Yusuf Leblebici",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 ; Conference date: 17-02-2019 Through 21-02-2019",

year = "2019",

month = mar,

day = "6",

doi = "10.1109/ISSCC.2019.8662505",

language = "English",

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Kim, G, Kull, L, Luu, D, Braendli, M, Menolfi, C, Francese, PA, Yueksel, H, Aprile, C, Morf, T, Kossel, M, Cevrero, A, Ozkaya, I, Burg, A, Toifl, T & Leblebici, Y 2019, 30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. in 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019., 8662505, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 2019-February, Institute of Electrical and Electronics Engineers Inc., pp. 476-478, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019, San Francisco, United States, 17/02/19. https://doi.org/10.1109/ISSCC.2019.8662505

30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. / Kim, Gain; Kull, Lukas; Luu, Danny et al.
2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 476-478 8662505 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Braendli, Matthias

AU - Menolfi, Christian

AU - Francese, Pier Andrea

AU - Yueksel, Hazar

AU - Aprile, Cosimo

AU - Morf, Thomas

AU - Kossel, Marcel

AU - Cevrero, Alessandro

AU - Ozkaya, Ilter

AU - Burg, Andreas

AU - Toifl, Thomas

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AB - The increasing demand on bandwidth for communicating among processors through wired interconnects in large-scale servers motivates the increase in the lane-data-rate from the current 28Gb/s to 56Gb/s or further. Recently published works [1]-[3] demonstrated ADC-based receiver (RX) prototypes equalizing > 56 Gb/s PAM-4 symbols for legacy channels with pre-FEC BERs of less than 2E-4 satisfying IEEE p802.bj/bs pre-FEC BER requirements. While the ADC-based > 56 Gb/s PAM-4 RXs provide strong equalization performance using a large number of feed-forward equalization (FFE) taps and a few decision-feedback equalization (DFE) taps [1], [2] implemented in digital, their power consumption remains excessive due to heavy arithmetic operations in the DSP.

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PB - Institute of Electrical and Electronics Engineers Inc.

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Kim G, Kull L, Luu D, Braendli M, Menolfi C, Francese PA et al. 30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. In 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 476-478. 8662505. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2019.8662505

30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

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