Abstract
Tiny surveillance robots need to efficiently compute a perception front-end workload, consisting of a neural network inference stack, and a localization back-end workload implementing a set of state-space equations. Miniaturization and low-power actuation make bristle robots [1] attractive locomotion platforms, but size limits lead to stringent energy constraints. The edge accelerator needs low leakage for long retentive stretches and efficient matrix compute for active bursts. We present a 0.84TOPS/W, 110μW retentive-sleep-capable resistive random-access memory (RRAM)-based accelerator in 40nm with 10 very long instruction word (VLIW)-controlled nonvolatile memory (NVM) matrix units (NMUs) with, in total, 5MB of RRAM, combined with a 10T SRAM-based state-update accelerator enabled by in-place memory updates. At VMIN, the design improves NVM access energy to 0.256pJ/b and peak NVM bandwidth to 12.8GB/s.
| Original language | English |
|---|---|
| Title of host publication | 2024 IEEE International Solid-State Circuits Conference, ISSCC 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 482-484 |
| Number of pages | 3 |
| ISBN (Electronic) | 9798350306200 |
| DOIs | |
| State | Published - 2024 |
| Event | 2024 IEEE International Solid-State Circuits Conference, ISSCC 2024 - San Francisco, United States Duration: 18 Feb 2024 → 22 Feb 2024 |
Publication series
| Name | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
|---|---|
| ISSN (Print) | 0193-6530 |
Conference
| Conference | 2024 IEEE International Solid-State Circuits Conference, ISSCC 2024 |
|---|---|
| Country/Territory | United States |
| City | San Francisco |
| Period | 18/02/24 → 22/02/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
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