29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification

Jong Hyeok Yoon; Muya Chang; Win San Khwa; Yu Der Chih; Meng Fan Chang; Arijit Raychowdhury

doi:10.1109/ISSCC42613.2021.9365926

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification

Jong Hyeok Yoon
, Muya Chang
, Win San Khwa
, Yu Der Chih
, Meng Fan Chang
, Arijit Raychowdhury

Department of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

90 Scopus citations

Abstract

As memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) higher bit-density (2-4× of SRAM), (2) CMOS process/voltage compatibility, (3) nano-second read (RD) and (4) non-volatility has emerged as a promising candidate [1]. In spite of early prototypes, several technology challenges remain, and need to be addressed through circuittechnology co-design [1]. This paper presents a 64Kb RRAM macro supporting: (1) a programmable (1 to 9) number of row-accesses (N) to enable vector-matrix multiplication (referred to as compute-in-memory, or CIM) for a target algorithm-level inference-accuracy [2] -[8], (2) voltage-based RD with active feedback, advancing the state-of-the-art current-based RD, targeted for the low ratio between the high-resistancestate (HRS) and low-resistance-state (LRS) in typical RRAM, (3) RD-disturb tolerance under RRAM drift, through embedded RD-disturb monitor and write (WR)-back and (4) in-situ WR verification to enable a tight resistance distribution.

Original language	English
Title of host publication	2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	404-406
Number of pages	3
ISBN (Electronic)	9781728195490
DOIs	https://doi.org/10.1109/ISSCC42613.2021.9365926
State	Published - 13 Feb 2021
Event	2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - San Francisco, United States Duration: 13 Feb 2021 → 22 Feb 2021

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	64
ISSN (Print)	0193-6530

Conference

Conference	2021 IEEE International Solid-State Circuits Conference, ISSCC 2021
Country/Territory	United States
City	San Francisco
Period	13/02/21 → 22/02/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Access to Document

10.1109/ISSCC42613.2021.9365926

Cite this

Yoon, J. H., Chang, M., Khwa, W. S., Chih, Y. D., Chang, M. F., & Raychowdhury, A. (2021). 29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. In 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers (pp. 404-406). Article 9365926 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 64). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC42613.2021.9365926

Yoon, Jong Hyeok ; Chang, Muya ; Khwa, Win San et al. / 29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2021. pp. 404-406 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{b91328074dca4920b0fd4af557af066f,

title = "29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification",

abstract = "As memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) higher bit-density (2-4× of SRAM), (2) CMOS process/voltage compatibility, (3) nano-second read (RD) and (4) non-volatility has emerged as a promising candidate [1]. In spite of early prototypes, several technology challenges remain, and need to be addressed through circuittechnology co-design [1]. This paper presents a 64Kb RRAM macro supporting: (1) a programmable (1 to 9) number of row-accesses (N) to enable vector-matrix multiplication (referred to as compute-in-memory, or CIM) for a target algorithm-level inference-accuracy [2] -[8], (2) voltage-based RD with active feedback, advancing the state-of-the-art current-based RD, targeted for the low ratio between the high-resistancestate (HRS) and low-resistance-state (LRS) in typical RRAM, (3) RD-disturb tolerance under RRAM drift, through embedded RD-disturb monitor and write (WR)-back and (4) in-situ WR verification to enable a tight resistance distribution.",

author = "Yoon, \{Jong Hyeok\} and Muya Chang and Khwa, \{Win San\} and Chih, \{Yu Der\} and Chang, \{Meng Fan\} and Arijit Raychowdhury",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 ; Conference date: 13-02-2021 Through 22-02-2021",

year = "2021",

month = feb,

day = "13",

doi = "10.1109/ISSCC42613.2021.9365926",

language = "English",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "404--406",

booktitle = "2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers",

}

Yoon, JH, Chang, M, Khwa, WS, Chih, YD, Chang, MF & Raychowdhury, A 2021, 29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. in 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers., 9365926, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 64, Institute of Electrical and Electronics Engineers Inc., pp. 404-406, 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, United States, 13/02/21. https://doi.org/10.1109/ISSCC42613.2021.9365926

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. / Yoon, Jong Hyeok; Chang, Muya; Khwa, Win San et al.
2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2021. p. 404-406 9365926 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 64).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification

AU - Yoon, Jong Hyeok

AU - Chang, Muya

AU - Khwa, Win San

AU - Chih, Yu Der

AU - Chang, Meng Fan

AU - Raychowdhury, Arijit

PY - 2021/2/13

Y1 - 2021/2/13

N2 - As memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) higher bit-density (2-4× of SRAM), (2) CMOS process/voltage compatibility, (3) nano-second read (RD) and (4) non-volatility has emerged as a promising candidate [1]. In spite of early prototypes, several technology challenges remain, and need to be addressed through circuittechnology co-design [1]. This paper presents a 64Kb RRAM macro supporting: (1) a programmable (1 to 9) number of row-accesses (N) to enable vector-matrix multiplication (referred to as compute-in-memory, or CIM) for a target algorithm-level inference-accuracy [2] -[8], (2) voltage-based RD with active feedback, advancing the state-of-the-art current-based RD, targeted for the low ratio between the high-resistancestate (HRS) and low-resistance-state (LRS) in typical RRAM, (3) RD-disturb tolerance under RRAM drift, through embedded RD-disturb monitor and write (WR)-back and (4) in-situ WR verification to enable a tight resistance distribution.

AB - As memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) higher bit-density (2-4× of SRAM), (2) CMOS process/voltage compatibility, (3) nano-second read (RD) and (4) non-volatility has emerged as a promising candidate [1]. In spite of early prototypes, several technology challenges remain, and need to be addressed through circuittechnology co-design [1]. This paper presents a 64Kb RRAM macro supporting: (1) a programmable (1 to 9) number of row-accesses (N) to enable vector-matrix multiplication (referred to as compute-in-memory, or CIM) for a target algorithm-level inference-accuracy [2] -[8], (2) voltage-based RD with active feedback, advancing the state-of-the-art current-based RD, targeted for the low ratio between the high-resistancestate (HRS) and low-resistance-state (LRS) in typical RRAM, (3) RD-disturb tolerance under RRAM drift, through embedded RD-disturb monitor and write (WR)-back and (4) in-situ WR verification to enable a tight resistance distribution.

UR - https://www.scopus.com/pages/publications/85102335279

U2 - 10.1109/ISSCC42613.2021.9365926

DO - 10.1109/ISSCC42613.2021.9365926

M3 - Conference contribution

AN - SCOPUS:85102335279

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 404

EP - 406

BT - 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021

Y2 - 13 February 2021 through 22 February 2021

ER -

Yoon JH, Chang M, Khwa WS, Chih YD, Chang MF, Raychowdhury A. 29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. In 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2021. p. 404-406. 9365926. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC42613.2021.9365926

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification

Abstract

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