TY - JOUR
T1 - 10-315-MHz cascaded hybrid phase-locked loop for pixel clock generation
AU - Song, Minyoung
AU - Kwak, Young Ho
AU - Ahn, Sunghoon
AU - Park, Hojin
AU - Kim, Chulwoo
PY - 2013
Y1 - 2013
N2 - A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70p spp , respectively, with a multiplication factor of 1024.
AB - A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70p spp , respectively, with a multiplication factor of 1024.
KW - All-digital phase-locked loop
KW - jitter reduction
KW - pixel clock generation
KW - time-to-digital converter
UR - http://www.scopus.com/inward/record.url?scp=84884881922&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2012.2227068
DO - 10.1109/TVLSI.2012.2227068
M3 - Article
AN - SCOPUS:84884881922
SN - 1063-8210
VL - 21
SP - 2080
EP - 2093
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 11
M1 - 6380633
ER -